The present invention relates to a power converter apparatus. In particular, the invention relates to a semiconductor device (power semiconductor module) having a semiconductor circuit that converts an alternating current to a direct current or to a power converter apparatus (inverter apparatus) having a capacitor module that forms a DC smoothing circuit in the power semiconductor module, where its interconnection inductance is required to be reduced.
Japanese Laid-Open Patent Publication No. 2006-318953 discloses a connection structure of terminals of semiconductor apparatus that reduces the inductance of a pair of interconnection members connected to a pair of electrode terminals of an external apparatus. The interconnection members of the above publication are shaped like plates, and arranged to be adjacent to face each other. The flowing directions of currents in the interconnection members are opposite to each other. The interconnection members are joined to the electrode terminals of the semiconductor apparatus to be connected to the interconnection members by ultrasonic bonding, resistance welding, or soldering. A pair of the electrode terminals of the external apparatus are exemplified by the positive terminal and the negative terminal of a capacitor.
Japanese Laid-Open Patent Publication No. 2005-347561 discloses a structure and a configuration that reduce the inductance in each of the internal wiring of a power semiconductor module, the internal wiring of a capacitor module, and the external wiring from the capacitor module to the semiconductor module. Japanese Laid-Open Patent Publication No. 2005-347561 discloses a plurality of insulated substrates 72 provided on a base 71 as shown in FIGS. 11A and 11B. A switching chip 73 and a diode chip 74 are provided on each insulated substrate 72. A positive conductor 75 and a negative conductor 76 are laminated, while being insulated from each other, on the top surface of each of the switching chip 73 and the diode chip 74. An insulation case (not shown) is arranged over the base 71 to cover the insulated substrates 72, the switching chips 73, the diode chips 74, the positive conductor 75, and the negative conductor 76. The positive conductor 75 and the negative conductor 76 include flat plate-like main conductors 75a, 76a and belt-like sub-conductors 75b, 76b formed at ends of the main conductors 75a, 76a, respectively. The sub-conductor 75b of the positive conductor 75 and the sub-conductor 76b of the negative conductor 76 are adjacent to each other while being insulated from each other, and form external terminals P2, N2, respectively. Japanese Laid-Open Patent Publication No. 2005-347561 also discloses an inverter apparatus in which a capacitor module is located on an insulation case of the a power semiconductor module. The capacitor module includes a positive conductor and a negative conductor that are connected to a capacitor element. The positive and negative conductors are each formed by a plate-like main conductor and belt-like sub-conductors. The two plate-like main conductors are laminated together, while being insulated from each other. The belt-like sub-conductors are provided at ends of the main conductors and laminated together, while being insulated from each other. Ends of the sub-conductors form the external connecting terminals. Japanese Laid-Open Patent Publication No. 2005-347561 further discloses an inverter apparatus having branched conductors each provided in an upright state on one of the main conductors 75a and 76a of the positive conductor 75 and the negative conductor 76. Each branched conductor has a branched conductor connected to the capacitor element.
Although Japanese Laid-Open Patent Publication No. 2006-318953 discloses a semiconductor apparatus that reduces the interconnection inductance of the wiring between a capacitor and joint portions of the external terminals of a semiconductor module, the publication discloses no configuration for reducing the inductance of the interior of the semiconductor module. Further, Japanese Laid-Open Patent Publication No. 2006-318953 discloses no structure of a semiconductor apparatus in which a capacitor is accommodated in a case.
Japanese Laid-Open Patent Publication No. 2005-347561 discloses a configuration that reduces the inductance in each of the internal wiring of a power semiconductor module and the internal wiring of a capacitor module, and a configuration that reduces the inductance of external connecting terminals. Japanese Laid-Open Patent Publication No. 2005-347561 also discloses a configuration in which a capacitor module is accommodated in an insulation case of a power semiconductor module.
In the manufacturing process of the inverter apparatus of Japanese Laid-Open Patent Publication No. 2005-347561, in which a capacitor module is accommodated in an insulation case of a power semiconductor module, the terminals of an interconnection member need to be joined to wiring patterns of an insulated substrate with the capacitor mounted on the interconnection member. If the joint is achieved by soldering, the temperature is significantly increased in the vicinity of the capacitor. Accordingly, a special capacitor with enhanced heat resistance needs to be used. However, Japanese Laid-Open Patent Publication No. 2005-347561 has no disclosure regarding the need for such a special capacitor. Also, Japanese Laid-Open Patent Publication No. 2005-347561 has no disclosure whatsoever about whether the insulated substrate 72 is joined by soldering to the connecting conductors that connect the positive conductor 75 and the negative conductor 76 to the insulated substrate 72. However, since it is assumed that soldering is used from the shape of the illustrated connecting conductor, a special capacitor with enhanced heat resistance needs to be used.